You Can’t Control what you Can’t Measure, OR Why it’s Close to Impossible to Guarantee Real-time Software Performance on a CPU with on-chip cache

1. Abstract Steady increases in CPU core speeds continue to extend the range of applications for computer-based solutions, resulting in the creation of ever more responsive systems. At these higher core speeds, on-chip cache architectures are used to prevent the CPU from stalling when accessing relatively slow off-chip memory. In normal operation, most fetch-execute cycles occur internally, guaranteeing the execution of the maximum instructions per second. However, this also serves to hide the state of executing code from the user. Given the fact that it is not possible to directly monitor the execution of code within such a CPU when it is running at full speed, is it possible to guarantee and control the performance of Real-Time software on these cache-based CPU architectures? This paper investigates this issue by first offering a definition of Real-Time software, together with a discussion on what must be done to prove that the system will meet its performance objectives in all circumstances. In addition, the range of software performance monitoring techniques that are currently available will be discussed, together with a summary of the pros and cons of each measurement technique. The conclusion of this paper is that it is close to impossible to make deterministic software performance measurements using traditional techniques on a CPU that heavily utilizes on-chip cache, so it is therefore almost impossible to guarantee the performance of Real-Time software based on these styles of microprocessor architectures unless new measurement techniques are utilized. Real-Time software is distinguished from any other application by the fact that performance criteria are included in the specifications. This means that for Real-Time software to be verified as being correct, it has to be proven that the software will always meet its performance objectives. With cache based microprocessor architectures, software performance measurements are extremely difficult to do without causing serious perturbations, affecting measurement accuracy. This holds true across all possible measurement techniques. Accurate, hardware only performance measurements are generally not possible on architectures utilizing on-chip cache. Software performance measurement techniques range from hardware assisted solutions, to software only ones. All techniques, however, rely on being able to get information about the current state of the executing code off-chip. Pure hardware or hardware assisted solutions such as Logic Analyzers (LAs), In Circuit Emulators (ICEs), or dedicated pure software performance monitoring devices cannot determine what code is executing in the cache-based CPU core by monitoring external microprocessor signals. It …